SAN MATEO, Calif., Nov. 28, 2017 /PRNewswire/ — At the 7th RISC-V Workshop today, SiFive, the first fabless provider of customized, open-source-enabled semiconductors, announced a number of new partnerships and products that exemplify the company’s rapid growth over the past year. These announcements provide further proof of SiFive’s leadership in aligning with industry leaders to spur innovation in the plateauing semiconductor industry as well as the company’s ability to meet increased demand for open access to custom silicon. The adoption of SiFive’s RISC-V Core IP continues to grow, with more than 150 evaluation licenses in progress.
SiFive news and activities at the workshop include:
An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based Freedom Unleashed 500 (U500) platform and Microsemi’s PolarFire FPGAs. (See related press release, “SiFive and Microsemi Expand Relationship with Strategic Roadmap Alignment and a Linux-Capable, RISC-V Development Board.”) Membership in GLOBALFOUNDRIES’ FDXcelerator Partner Program: SiFive has joined the GF program that brings together select partners to integrate their products or services into validated, plug-and-play design solutions. This provides GF customers access to SiFive RISC-V Core IP alongside a broad set of quality offerings specific to GF’s 22FDX technology. OnChip demonstration: SiFive partner OnChip will unveil and demonstrate a suite of IP to support analog peripherals and an always-on power domain, which will be available through the DesignShare program to create mixed-signal RISC-V SoCs.
The news comes on the heels of SiFive’s recent release of the industry’s first RISC-V based Linux core: U54-MC Coreplex IP, a 64-bit, quadcore real-time capable application processor with support for full featured operating systems. The standard U54-MC Coreplex contains four U54 CPUs along with a single E51 CPU, and is the first commercial RISC-V core to include multicore support and cache coherence.
SiFive also forged a string of new partnerships recently including:
SEGGER Microcontroller: SEGGER in September added support for SiFive’s Coreplex IP to its J-Link debug probe, making it the first commercial debugging tool available for RISC-V cores. Lauterbach: In October, Lauterbach partnered with SiFive to bring TRACE32 support for high-performance RISC-V cores, providing multicore debugging on individual hardware threads of SiFive cores, enabling debugging right from the reset vector, which analyzes startup codes and other key functions.
Both products will be available for demos at the 7th RISC-V Workshop.
In addition to new